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256Mx72 bits
DDR2 SDRAM Registered DIMM
HYMP125R72(L)M4
Revision History
No. 0.1 0.2 Initial Release Corrected IDD Spec. Corrected Pin assignment table & SPD typo(#42) History Draft Date Mar. 2004 May. 2004 July 2004 Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2004 1
256Mx72 bits
DDR2 SDRAM Registered DIMM
HYMP125R72(L)M4
DESCRIPTION
Hynix HYMP125R72(L)M4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix HYMP125R72(L)M4 series consists of eighteen 256Mx4 DDR2 SDRAMs in 63-ball FBGA Dual Die Package(DDP)s. Hynix HYMP125R72(L)M4 series provide a high performance 8-byte interface in 133.35mm width form factor of industry stanard. It is suitable for easy interchange and addition. HYMP125R72(L)M4 series is designed for high clock speed of up to 266MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMP125R72(L)M4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
* * 2GB (256M x 72) Registered DDR2 DIMM based on 256Mx4 DDR2 DDP SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply JEDEC Standard 240-pin dual in-line memory module (DIMM) Data Error Check Correction (ECC) Capability All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) * * * * * * Fully differential clock operations (CK & /CK) with 200MHz / 266MHz Programmable CAS Latency 3 / 4 / 5 supported Programmable Burst Length 4 / 8 with both sequential and interleave mode All inputs and outputs SSTL_1.8 compatible Auto refresh and self refresh supported 7.8us refresh period at Lower than TCASE 85, 3.9us( 85 TCASE 95) * * Serial Presence Detect(SPD) with EEPROM Package: 63ball FBGA(DDP)
* * * *
ORDERING INFORMATION
Type
PC2-3200 (DDR2-400) PC2-4300 (DDR2-533)
Part No.
HYMP125R72(L)M4-E4 HYMP125R72(L)M4-E3 HYMP125R72(L)M4-C5 HYMP125R72(L)M4-C4
Description / component
CL-tRCD-tRP
4-4-4
Form Factor
2 ranked 2GB Reg. DIMM HY5PS1G421(L)M * 18EA
3-3-3 5-5-5 4-4-4
240pin Registered DIMM 133.35 mm x 30,00 mm
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2004 2
HYMP125R72(L)M4
Input/Output Functional Description
Symbol CK0~CK1 Type IN Polarity Positive Edge Negative Edge Active High Pin Description Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0~CK1
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE0~CKE1
IN
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 On-Die Termination signals. When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
S0~S1
IN
Active Low
ODT0~ODT1 RAS, CAS, WE Vref VDDQ BA0~BA1
IN IN Supply Supply IN
Active High Active Low
-
Selects which DDR2 SDRAM internal bank of four is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins.
A0~A9,A10/AP A11~A13
IN
-
DQ0~DQ63, CB0~CB7
IN
-
DM0~DM8
IN
Active High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.
VDD,VSS
Supply Positive Edge Negative Edge -
DQS0~DQS17
I/O
Positive line of the differential data strobe for input and output data
DQS0~DQS17
I/O
Negative line of the differential data strobe for input and output data
SA0~SA1
IN
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Parity bit for the Address and Control bus("1". Odd, "0".Even) Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs)
SDA
I/O
-
SCL
IN
-
VDDSPD
Supply
RESET
IN
Par_In Err_Out TEST
IN OUT
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HYMP125R72(L)M4
PIN ASSIGNMENT
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Key VSS VSS VDD NC,Err_Out VDD A10/AP BA0 VDDQ WE CAS VDDQ NC, S1 NC, ODT1 VDDQ VSS DQ32 Name VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD BA2,NC NC,Err_Out VDDQ A11 A7 VDD A5 A4 VDDQ A2 VDD Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC(TEST) VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Name VSS DQ4 DQ5 VSS DM0/DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 DQS10 VSS RFU RFU VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 DQS12 VSS DQ30 DQ31 VSS 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Key CK0 CK0 VDD A0 VDD BA1 VDDQ RAS S0 VDDQ ODT0 A13,NC VDD VSS DQ36 DQ37 Name CB4 CB5 VSS DM8,DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC,CKE1 VDD A15,NC A14,NC VDDQ A12 A9 VDD A8 A6 VDDQ A3 A1 VDD Pin 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name VSS DM4/DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC,DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC,DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)
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HYMP125R72(L)M4
FUNCTIONAL BLOCK DIAGRAM
VSS /RS0 /RS1
SCL
SCL WP
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D9,D27(DDP) I/O2 I/O3
DQS0 /DQS0 DQ0 DQ1 DQ2 DQ3
DQS1 /DQS1 DQ8 DQ9 DQ10 DQ11
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D1,D19(DDP) I/O2 I/O3
DQS9 /DQS9
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D0,D18(DDP) I/O2 I/O3
Serial PD A1 SA1
A1 SA2
SDA
A0 SA0
V DD SPD V DD /VDDQ
DQ4 DQ5 DQ6 DQ7
DQS10 /DQS10 DQ12 DQ13 DQ14 DQ15
Serial PD DO-D35 DO-D35 DO-D35
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D10,D28(DDP) I/O2 I/O3
V REF V SS
/RS0 /RS1
DQS2 /DQS2 DQ16 DQ17 DQ18 DQ19
DQS3 /DQS3 DQ24 DQ25 DQ26 DQ27
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D3,D21(DDP) I/O2 I/O3
DQS11 /DQS11
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D2,D20(DDP) I/O2 I/O3
CK0
DQ20 DQ21 DQ22 DQ23
DQS12 /DQS12 DQ28 DQ29 DQ30 DQ31
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D11,D29(DDP) I/O2 I/O3
/CK0
P L L
PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD35 /PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD35 PCK7 ==> CK: Register
/RESET
OE
/PCK7 ==> /CK: Register
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D12,D30(DDP) I/O2 I/O3
Signals for Address and Command Parity Function
Register
DQS8 /DQS8 CB0 CB1 CB2 CB3
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D8,D26(DDP) I/O2 I/O3
DQS17 /DQS17 CB4 CB5 CB6 CB7
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D17,D35(DDP) I/O2 I/O3
PARIN /PTYERR
PAR_IN
Register
PARIN /PTYERR
/Err_Out
/RS0 /RS1
DQS4 /DQS4 DQ32 DQ33 DQ34 DQ35
DQS5 /DQS5 DQ40 DQ41 DQ42 DQ43
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D5,D23(DDP) I/O2 I/O3
DQS13 /DQS13
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D4,D2(DDP) I/O2 I/O3
PAR_IN and /Err_Out are connected with the only one Register.
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D13,D31(DDP) I/O2 I/O3
DQ36 DQ37 DQ38 DQ39
DQS14 /DQS14 DQ44 DQ45 DQ46 DQ47
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D14,D32(DDP) I/O2 I/O3
/RS0 /RS1
DQS6 /DQS6 DQ48 DQ49 DQ50 DQ51
DQS7 /DQS7 DQ56 DQ57 DQ58 DQ59
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D7,D25(DDP) I/O2 I/O3
DQS15 /DQS15
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D6,D24(DDP) I/O2 I/O3
DQ52 DQ53 DQ54 DQ55
DQS9 /DQS9 DQ60 DQ61 DQ62 DQ63
DM /CS DQS /DQS DM /CS DQS /DQS I/O0 I/O1 D15,D33(DDP) I/O2 I/O3
DM /CS DQS /DQS DM /CS DQS I/O0 I/O1 D9,D34(DDP) I/O2 I/O3
/S0* /S1* BA0 to BA1
A0 to A13 /RAS /CAS
/WE CKE0 CKE1 ODT0
ODT1
1:2 R E G I S T E R
/RST
/RS0 to /CS0 :SDRAMs D0 to D17 /RS1 to /CS1 :SDRAMs D18 to D35 RBA0 - RBA1 ==> BA0 - BA1: SDRAMs D0 to D35
/RA0 - RA13 ==> A0 to A13: SDRAMs D0 to D35
/RRAS ==>/RAS: SDRAMs D0 to D35 /RCAS ==>/CAS: SDRAMs D0 to D35
/RWE ==>/WE: SDRAMs D0 to D35
RCKE0 ==> CKE0: SDRAMs D0 to D17
Notes:
1. DQ-to-I/O wiring shown as recommanded but may be changed. 2, Unless otherwise noted, resistor value are 22 Ohms +/- 5%. 3. /RS0 and /RS1 alternate between the back and front sides of the DIMM. * : /S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers. **: /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers.
RCKE1 ==> CKE1: SDRAMs D18 to D35 RODT0 ==> ODT0: SDRAMs D0 to D17
RODT1 ==> ODT1: SDRAMs D0 to D35
/RESET** PCK7**
/PCK7**
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HYMP125R72(L)M4
ABSOLUTE MAXIMUM RATINGS
Parameter Operating temperature(ambient) DRAM Component Case Temperature Range Operating Humidity(relative) Storage Temperature Storage Humidity(without condensation) Barometric Pressure(operating & storage) Symbol TOPR TCASE HOPR TSTG HSTG PBAR Value 0 ~ +55 0 ~+95 10 to 90 -50 ~ +100 5 to 95 105 to 69
o o
Unit C C 1 2 1 1 1
Note
%
o o
C C
K Pascal
1,3
Note : 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. 3. Up to 9850 ft.
Operating Condtions(AC&DC)
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter Symbol VDD Power Supply Voltage VDDQ Input Reference Voltage EEPROM Supply Voltage Termination Voltage VREF VDDSPD VTT 1.7 0.49 x VDDQ 1.7 VREF-0.04 1.9 0.51 x VDDQ 3.6 VREF+0.04 V V V V 3 1 2 Min 1.7 Max 1.9 Unit V Note
Note :
1.VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device.
Input DC Logic Level
Parameter Input High Voltage Input Low Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Note
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HYMP125R72(L)M4
Input AC Logic Level
Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) Min VREF + 0.250 Max VREF - 0.250 Unit V V Note
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Notes: 1. 2. 3. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. The input signal minimum slew rate is to be maintained over the range from VIL(dc) max to VIH(ac) min for rising edges and the range from VIH(dc) min to VIL(ac) max for falling edges as shown in the below figure. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 V V V/ns Units 1 1 2, 3 Notes
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
VSWING(MAX)
VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
delta TF Falling Slew = VIH(dc) min - VIL(ac) max delta TF
delta TR Rising Slew = VIH(ac) min - VIL(dc) max delta TR
< Figure : AC Input Test Signal Waveform >
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HYMP125R72(L)M4
Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Parameter ac differential input voltage ac differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6 0.5 * VDDQ + 0.175 Units V V Notes 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. Crossing point
VIX or VOX
Differential AC output parameters
Symbol VOX (ac) Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Notes 1
Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
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HYMP125R72(L)M4
Output Buffer Levels
Output AC Test Conditions
Symbol VOH VOL VOTR Parameter Minimum Required Output Pull-up under AC Test Load Maximum Required Output Pull-down under AC Test Load Output Timing Measurement Reference Level SSTL_18 Class II VTT + 0.603 VTT - 0.603 0.5 * VDDQ Units V V V 1 Notes
1. The VDDQ of the device under test is referenced.
Output DC Current Drive
Symbol IOH(dc) IOL(dc) 1. 2. 3. 4. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 Class II - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. The dc value of VREF applied to the receiving device is set to VTT The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement.
OCD defalut characteristics
Description
Output impedance Pull-up and pull-down mismatch Output slew rate Sout
Parameter
Min
12.6 0 1.5
Nom
18
Max
23.4 4
Unit
ohms ohms V/ns
Notes
1,2 1,2,3 1,4,5,6
-
5
Note: 1. Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. 6. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins. Output slew rate at 667&800MT/s will be added with JEDEC process.
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HYMP125R72(L)M4
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz )
Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance CK0, /CK0 CKE, ODT /CS Address, /RAS, /CAS, /WE DQ,DM,DQS, /DQS Pin Symbol CCK CI1 CI2 CI2 CIO Min 9 10 10 10 10 Max 13 15 15 15 15 Unit pF pF pF pF pF
Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only.
IDD Specifications
HYMP125R72(L)M4 Parameter
Operating one bank active-precharge current Operating one bank active-read-precharge current Precharge power-down current Precharge quiet standby current Precharge standby current
PC2 3200 Symbol
IDD0
PC2 4300 max.
4000
max.
3640
Unit
mA
Note
IDD1 IDD2P IDD2Q IDD2N IDD3P(F)
3820
4180
mA
1408 2380 2560 1840 704 3100 4540 4540 4780 880 808 5800
1444 2560 2740 2020 722 3460 4900 4900 4960 880 808 6340
mA mA mA mA mA mA mA mA mA mA mA mA
Active power-down current IDD3P(S) Active Standby Current Operating burst read current Operating Current Burst auto refresh current IDD3N IDD4R IDD4W IDD5B IDD6 Self Refresh Current IDD6(L) Operating bank interleave read current IDD7
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HYMP125R72(L)M4
IDD Meauarement Conditions
Symbol IDD0 Conditions
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
Units
mA
IDD1
mA
IDD2P IDD2Q IDD2N
mA
mA
mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
IDD4W
mA
IDD4R
mA
IDD5B
mA
IDD6
mA
IDD7
mA
Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.2 / July 2004 11
HYMP125R72(L)M4
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed Bin(CL-tRCD-tRP) Parameter CAS Latency tRCD tRP tRC tRAS DDR2-533(C4) 4-4-4 min 4 15 15 60 45 DDR2-533(C5) 5-5-5 min 5 18.75 18.75 63.75 45 DDR2-400(E3) 3-3-3 min 3 15 15 55 40 DDR2-400(E4) 4-4-4 min 4 20 20 65 45 ns ns ns ns ns Unit
AC Timing Parameters by Speed Grade
DDR2-400 Parameter Symbol Min Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew Clock High Level Width Clock Low Level Width Clock Half Period System Clock Cycle Time DQ and DM input hold time DQ and DM input setup time Control & Address input Pulse Width for each input DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time tAC tDQSCK tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD -600 -500 0.45 0.45 min (tCL,tCH) 5000 400 400 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 Max 600 500 0.55 0.55 8000 tAC max tAC max tAC max 350 450 WL + 0.25 Min -500 -500 0.45 0.45 min (tCL,tCH) 3750 350 350 0.6 0.35 tAC min 2*tAC min tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 Max 500 450 0.55 0.55 8000 tAC max tAC max tAC max 300 400 WL + 0.25 ps ns CK CK ns ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK 1 1 DDR2-533 Unit Note
Rev. 0.2 / July 2004
12
HYMP125R72(L)M4
- continued DDR2 400 Parameter Symbol Min Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay CAS to CAS command delay Write recovery time Auto Precharge Write Recovery + Precharge Time Write to Read Command Delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off
t
DDR2 533 Unit Max 0.6 1.1 0.6 Min 0.4 0.25 500 500 0.9 0.4 Max 0.6 1.1 0.6 tCK tCK ps ps tCK tCK Note
tWPST tWPRE tIH tIS tRPRE tRPST
0.4 0.25 600 600 0.9 0.4
tRFC
tRRD tCCD tWR tDAL
105
7.5 2 15 (tWR/tCK) + (tRP/tCK) 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) tAC(min)+2 2.5 tAC(min)
-
105
7.5 2
-
ns
ns tCK
-
15 (tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10
-
ns tCK
tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
t
-
-
ns ns ns
-
200 2 2 6 - AL 3
-
tCK tCK tCK tCK tCK
CKE
AOND
t
2 tAC(max)+1 2tCK+tAC(max )+1 2.5 tAC(max)+ 0.6
2 tAC(min) tAC(min)+2 2.5 tAC(min)
2 tAC(max)+1 2tCK+tAC(max )+1 2.5 tAC(max)+ 0.6
tCK ns ns tCK ns ns tCK tCK
AON
tAONPD tAOFD t
AOF
ODT turn-off (Power-Down mode)
ODT to power down entry latency
t
AOFPD tANPD tAXPD tOIT tDelay tREFI tREFI
tAC(min)+2 3 8 0 tIS+tCK+tIH
2.5tCK+tAC( max)+1
tAC(min)+2 3 8
2.5tCK+tAC( max)+1
ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval
12
0 tIS+tCK+tIH
12
ns ns
-
7.8
3.9
-
7.8
3.9
us us
2 3
Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G421(L)M). 2. 0C TCASE 85C 3. 85C TCASE 95C Rev. 0.2 / July 2004 13
HYMP125R72(L)M4
PACKAGE OUTLINE
Front
133.35
Side
4.0 max
R E G I S T E R
4.00.1
30.0
Detail-A
5.175
63.0
PLL
Detail-B
1.27 0.10
5.0
55.0 5.175
Back
17.80 10.0
R E G I S T E R
3.0
3.0
Detail of Contacts A
0.20
0.20
Detail of Contacts B
2.50
2.50
1.0
0.8 0.05
1.50 0.10 5.00
Note) All dimensions are typical millimeter scale unless otherwise stated.
Rev. 0.2 / July 2004
3.80
14
SERIAL PRESENCE DETECT
SPD SPECIFICATION
(256Mx72 Registered DDR2 DIMM)
Rev. 0.2 / July 2004
15
HYMP125R72(L)M4
SERIAL PRESENCE DETECT
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Function Description Number of bytes utilized by module manufacturer Total number of Bytes in SPD device Fundamental memory type Number of row address on this assembly Number of column address on this assembly Number of DIMM ranks Module data width Module data width (continued) Voltage Interface level of this assembly DDR SDRAM cycle time at CL=5 DDR SDRAM access time from clock (tAC) DIMM Configuration type Refresh Rate and Type Primary DDR SDRAM width Error Checking DDR SDRAM data width Reserved Burst Lengths Supported Number of banks on each SDRAM Device CAS latency supported Reserved DIMM Type DDR SDRAM module attributes DDR SDRAM device attributes : General DDR SDRAM cycle time at CL=4(tCK) DDR SDRAM access time from clock at CL=4(tAC) DDR SDRAM cycle time at CL=3(tCK) DDR SDRAM access time from clock at CL=3(tAC)
Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4), C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)
Speed Grade all all all all all all all all all E3,E4 C4,C5 E3,E4 C4,C5 all all all all all all all all all all E3,E4,C5 C4 E3,E4,C5 C4 E3,C4 E4,C5 E3,C4 E4,C5 E3, C4 E4 C5 all E3, C4 E4 C5 E3 E4,C4,C5 all E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 E3, E4 C4, C5 all E3, E4 C4, C5 all E3,E4,C4 C5 E3 C4 E4 C5 Function Supported 128 Bytes 256 Bytes DDR2 SDRAM 14 11 30.0 mm/ stack/ 2 rank 72 Bits SSTL 1.8V 5.0 ns 3.75 ns +/-0.6ns +/-0.5ns ECC 7.8us & Self refresh x4 x4 4,8 4 3, 4, 5 Regular RDIMM Normal Supports weak driver 5.0ns 3.75ns +/-0.6ns +/-0.5ns 5.0ns Undefined +/-0.6ns Undefined 15ns 20ns 18.75ns 7.5ns 15ns 20ns 18.75ns 40ns 45ns 1GB 0.6ns 0.5ns 0.6ns 0.5ns 0.40ns 0.35ns 0.40ns 0.35ns 15ns 10ns 7.5ns 7.5ns Undefined Undefined tRC extended 55ns 60ns 65ns 63.75ns Hexa Value 80 08 08 0E 0B 71 48 00 05 50 3D 60 50 02 82 04 04 00 0C 04 38 00 01 00 01 50 3D 60 50 50 00 60 00 3C 50 4B 1E 3C 50 4B 28 2D 01 60 50 60 50 40 35 40 35 3C 28 1E 1E 00 00 50 37 3C 41 3F Note
1 1
2 2
2 2 2 2
27 28 29
Minimum Row Precharge Time(tRP) Minimum Row Activate to Row Active delay(tRRD) Minimum RAS to CAS delay(tRCD)
30 31 32 33 34 35 36 37 38 39 40
Minimum active to precharge time(tRAS) Module rank density Address and command input setup time before clock (tIS) Address and command input hold time after clock (tIH) Data input setup time before clock (tDS) Data input hold time after clock (tDH) Write recovery time(tWR) Internal write to read command delay(tWTR) Internal read to precharge command delay(tRTP) Memory analysis probe characteristics Extension of byte 41 tRC and byte 42 tRFC
41
Minimum active / auto-refresh time ( tRC)
Rev. 0.2 / July 2004
16
HYMP125R72(L)M4
- continued Byte# 42 43 44 45 46 47~61 62 Function Description Minimum auto-refresh to active/auto-refresh command period(tRFC) Maximum cycle time (tCK max) Maximim DQS-DQ skew time(tDQSQ) Maximum read data hold skew factor(tQHS) PLL Relock time Superset information(may be used in future) SPD Revision code E3 E4 C4 C5 Speed Grade all all E3, E4 C4, C5 E3, E4 C4, C5 Function Supported 105ns 8.0ns 0.35ns 0.30ns 0.45ns 0.40ns 15us Undefined 1.0 Hynix JEDEC ID Hynix(Korea Area) HSA(United States Area) HSE(Europe Area) HSJ(Japan Area) Singapore Asia Area H Y M P 1 2 5 R 7 2 M 4 `-' E C 3 4 5 Blank Hexa Value 69 80 23 1E 2D 28 0F 00 10 5D E4 D7 BB AD 00 0* 1* 2* 3* 4* 5* 48 59 4D 50 31 32 35 52 37 32 4D 34 2D 45 43 33 34 35 20 Note
63
Checksum for Bytes 0~62
64 65~71
Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code
72
Manufacturing location
6
73 74 75 76 77 78 79 80 81 82 83 84 85 86
Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) -------- Manufacture part number(Hynix Memory Module) Manufacture part number (DDR2 SDRAM) ---------Manufacture part number(Memory density) Manufacture part number(Module Depth) ------- Manufacture part number(Module Depth) Manufacture part number(Module type) Manufacture part number(Data width) -------Manufacture part number(Data width) Manufacture part number(Component Package type) Manufacture part number(Component configuration) Manufacture part number(Hyphen) Manufacture part number(Minimum cycle time) E3, E4 C4, C5 E3 E4,C4 C5
87 88~90 91 92 93 94 95~98 99~127 128~255
-------Manufacture part number(Minimum cycle time) Manufacture part number(T.B.D) Manufacture revision code(for Component) Manufacture revision code (for PCB) Manufacturing date(Year) Manufacturing date(Week) Module serial number Manufacturer specific data (may be used in future) Open for customer use
Undefined Undefined
00 00
3 3 4 5 5
Note : 1. The bank address is excluded 2. This value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix's own Module Serial Number System 5. These bytes undefined and coded as `00h' 6. Refer to Hynix Web Site
Byte 84~85, Low Power Part
Byte # 84 85 Function Description Manufacture part number(Low power part) Manufacture part number(Component configuration) Speed Grade Function Supported L 4 Hexa Value 4C 34 Note
Rev. 0.2 / July 2004
17

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